MIPI DSI Bandwidth Calculator

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MIPI DSI Bandwidth Calculator

Metric	Value	Formula / Basis

Calculation Mode: Precise Timing Percentage Estimate

Active Width

Active Height

Color Depth (bpp) 16 18 24

Data Lanes 1 2 4

HFP

HSYNC

HBP

VFP

VSYNC

VBP

Blanking Percentage (%)

15%

Refresh Rate (Hz)

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TFT Display Timing

TFT Display Timing Visualizer

Watch the dot scan across the virtual frame to see how PCLK, HSYNC, VSYNC, and DE work together to draw an image on a screen.

Frame Scanning Area

DE Signal:

Speed:

Sync (H/V)

Back Porch

Active Data (DE)

Front Porch

Live Logic Signals

PCLK: Pixel Clock. Pulses once for every single pixel position.

DE: Data Enable. High ONLY when scanning the Active Data area.

HSYNC: Horizontal Sync. Pulses to start a new row.

VSYNC: Vertical Sync. Pulses to start a new frame.

What do these terms mean?

Front Porch (FP)

A brief delay after the active pixel data finishes, but before the sync pulse occurs. It gives the hardware a moment to stabilize.

Sync Pulse (HSYNC/VSYNC)

A signal telling the display panel to reset its drawing position back to the beginning of the next line (HSYNC) or back to the top-left (VSYNC).

Back Porch (BP)

A brief delay after the sync pulse ends, but before the actual pixel data begins. It provides settling time.

Active Area / Data Enable (DE)

The portion of the timing cycle where actual, visible pixels are drawn on the screen. The DE signal goes HIGH.

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How does a TFT Panel Work?

A Thin-Film-Transistor (TFT) display consists of a massive grid of pixels. To display an image, the screen can't light up all pixels simultaneously. Instead, it draws them one by one, scanning from left to right, and top to bottom (exactly like the visualizer above). The timing signals act as the conductor of this orchestra, ensuring the display panel knows exactly when and where to place the incoming color data.

GMSL2 Deserializer to TFT Signals

In modern systems (like automotive infotainment systems or remote industrial displays), video is often transmitted over long distances using a high-speed serial link like GMSL2 (Gigabit Multimedia Serial Link). A Serializer compresses the video at the source, sends it over a single cable, and a Deserializer translates it back into signals the TFT panel understands.

Here are the primary signals passed from the GMSL2 Deserializer to a traditional parallel RGB TFT panel:

1. Timing & Synchronization

• PCLK (Pixel Clock): The continuous heartbeat that clocks data into the display.
• VSYNC & HSYNC: The structural boundaries of the frame and lines.
• DE (Data Enable): Gates the active color data so the screen only draws when valid.

2. Video Data (RGB)

Parallel data lines carrying the color info. For a 24-bit display (RGB888), there are 24 physical wires representing Red, Green, and Blue intensities for the exact pixel currently being drawn.

3. Control Interfaces

Usually an I2C or SPI interface passed through the GMSL link. This allows the main processor to configure panel registers, adjust gamma, or read diagnostic information.

4. Backlight & Power

Hardware signals, often including a PWM (Pulse Width Modulation) pin to control screen brightness, an Enable pin to turn the display on/off, and standard power rails (VDD).

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The Brains of the Panel: The TCON

It's important to note that the signals from the GMSL2 Deserializer don't connect directly to the glass pixels. Instead, they feed into an IC usually located directly on the display module called the Timing Controller (TCON). The TCON acts as the ultimate conductor for the panel. It takes the standard logic-level signals (PCLK, Syncs, DE, and RGB data) and translates them into the precise, high-voltage analog signals required by the panel's Source and Gate drivers. If the TCON doesn't receive a valid DE signal (try toggling it off in the visualizer above!), it won't instruct the drivers to update the screen, resulting in a blank display.

*Note: Many modern displays use MIPI DSI or eDP instead of parallel RGB, which packages these timing syncs and data into high-speed data packets. I will add the MIPI DSI and eDP protocol details in the next blog post, stay tuned!

Reference: Click here to learn more about TFT Timing