MIPI Explained: How Data Travels Between Devices
A modern camera can generate millions of pixels every second, and a display needs to update those pixels continuously. How can all that information travel through just a few wires?
That's where MIPI comes in.
Why MIPI?
Older display interfaces such as RGB used many parallel data lines.
As display resolution increased, designers faced several challenges:
- More PCB routing
- Larger connectors
- Higher EMI
- Increased system cost
MIPI solves this by converting parallel data into high-speed serial data.
Instead of using dozens of signals, data is transmitted through a small number of high-speed lanes.
Two Parts of MIPI
Protocol Layer
The protocol decides:
- What data is being sent
- How it is organized
- How the receiver interprets it
Examples:
- CSI-2 for cameras
- DSI-2 for displays
You can think of the protocol layer as data packaging.
PHY Layer
The PHY decides:
- Voltage levels
- Timing
- Clocking
- Electrical signaling
You can think of the PHY layer as the transportation system.
D-PHY and C-PHY
D-PHY is the most commonly used MIPI physical layer.
Each lane consists of two signals:
- D+
- D-
The receiver looks at the voltage difference between the two wires rather than the voltage on a single wire.
This improves noise immunity and reduces EMI.
C-PHY is a newer MIPI physical layer designed to provide higher bandwidth with fewer connections.
Each lane consists of three signals:
- Dp or A
- Dn or B
- Dc or C
These three wires form a trio.
Unlike D-PHY, C-PHY does not use traditional differential pairs. Instead, the receiver looks at the relative voltage relationship between the three wires and decodes the data from the different signal states.
This allows more information to be transferred per symbol compared to D-PHY.
Benefits of C-PHY:
- Higher bandwidth with fewer pins
- Reduced connector size
- Better PCB routing efficiency
- Suitable for high-resolution cameras and displays
Common applications:
- High-resolution camera sensors
- 4K/8K displays
- Advanced automotive infotainment systems
- ADAS camera systems
DSI Example Calculation
Suppose we have:
Display Resolution = 1920 × 1080
Refresh Rate = 60 Hz
Color Depth = 24 bits/pixel
Pixel Rate:
1920 × 1080 × 60
= 124.4 Million Pixels/sec
Required Bandwidth:
124.4M × 24
= 2.98 Gbps
Ignoring protocol overhead, the display needs approximately 3 Gbps.
If we use:
4 D-PHY lanes
Bandwidth per lane:
3 Gbps ÷ 4
= 750 Mbps/lane
A 500 MHz DDR clock provides:
1 Gbps/lane
which is sufficient for this display.
What Does "Double Data Rate" Mean?
One thing that often confuses engineers is the D-PHY clock.
Suppose the clock lane operates at:
500 MHz
Data is transferred on:
- Rising edge
- Falling edge
Because data moves on both edges:
Data Rate = 2 × Clock Frequency
So:
500 MHz Clock = 1 Gbps per lane
This is called Double Data Rate (DDR).
The clock is 500 MHz, but the lane transfers 1 billion bits every second.
CSI Example Calculation
Consider a camera:
Resolution = 1920 × 1080
Frame Rate = 30 fps
RAW10 Format = 10 bits/pixel
Bandwidth:
1920 × 1080 × 30 × 10
= 622 Mbps
Including packet overhead and blanking, the requirement is typically around:
700 to 800 Mbps
With two D-PHY lanes:
800 Mbps ÷ 2
= 400 Mbps/lane
This is well within the capability of a standard D-PHY interface.
Real System Example
In a vehicle infotainment system:
Camera → CSI-2 → D-PHY → SoC
The camera sends image data to the processor.
The processor then generates display data:
SoC → DSI → D-PHY → Display
The protocol organizes the information.
The PHY moves the information.
Every frame shown on the display and every image captured by the camera follows this same basic path.
